OpenLane
OpenLane is an Open Source ASIC tool. You can download it from here. The installation instructions are pretty straight forwards and it takes about 15 minutes and 3GB of disk space.
For a lot of great information on how it works and what it does, please watch Mohamed Shalan’s OpenLane FOSSI dialup presentation
Here’s the overview:
We put our HDL in at one end, and out the other comes the GDS2 files that are the standard file format for the foundry.
The most fundamental steps are:
- Synthesis
- Floor planning
- Place and Route
- sign off: Layout vs Schematic, Design Rule Check, Static Timing Analysis
To see more about OpenLane’s output files - check this article
OpenLane makes a lot of use of OpenROAD. This is a project funded by DARPA to develop open source ASIC tooling.
You can watch some interviews I did with Tom Spyrou, lead dev of OpenROAD here.
Tom also did a presentation for OpenTapeOut.
Course feedback
The part I enjoyed the most was going back to the Verilog and seeing test benches pass. In particular the waveform viewer. At the latter parts of course you're simulating the entire Caravel system on chip with a RISCV core. Being able to drill down into everything inside that core, I can log the program counter, I can log all the address and data buses and you can just see in exquisite detail what the system is doing, and it's doing that because I programmed it. Being able to drill down into that detail was really fascinating.