Netlist
A netlist is a machine readable file that contains all the connections between all the components in your design.
They are one of the outputs of a Synthesis tool like Yosys.
These examples are taken from http://bygone.clairexen.net/yosys/screenshots.html
If you have a counter design written in an HDL like Verilog
module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule
The output netlist can be visualised like this:
You can see the blocks are fairly ‘high level’, like multiplexors ($mux), or adders ($add). These types of blocks are not part of the Skywater PDK, so they need to be broken down into more simple blocks.
These blocks are now simple enough that they can be mapped onto the standard cells we have in the PDK. The synthesis process is the first step in the OpenLane tool.
Course feedback
The Zero To ASIC course took me on a fantastic journey from drawing and simulating a MOSFET, formal verification leading up to implementing a custom design with an open PDK and completely open source tools. The course is crammed full of interesting material with great pacing and support from Matt, and it's been a fantastic opportunity to meet other folks with shared interests and different backgrounds. The course has left me excited with opportunities for new projects and optimism for some working silicon!