Caravel is the name of the harness provided by Efabless to make it easier to submit a design to the foundry. Among other things, it provides: The padring 3kB of memory A small RISCV processor called PicoRV32 GPIOs A logic analyser A Wishbone bus For the full details, check the documentation The simplest way to interface between your project and the PicoRV32 is probably the logic analyser. This gives you 128 ins and outs that you can use to configure or debug your design.

Efabless have announced MPW2! The closing date is the 18th of June. The biggest changes are: OpenLANE ASIC flow updated to rc0.15 Caravel has become caravel_user_project at the mpw-two-c tag: smaller repo size includes a ‘Caravel Lite’ submodule new IRQ ports logic analyser registers renamed The submission process has been streamlined to make it faster and easier to submit You can browse the current applications here: https://efabless.

In this interview Dan and I talk about his submission to the first shuttle, simulating video projects, how to do graphics with no frame buffer and the joys of retro gaming. Caravel repo: https://github.com/dan-rodrigues/caravel_vdp_lite IceStation32: https://github.com/dan-rodrigues/icestation-32

OpenLANE makes a lot of output files! This can be quite confusing when you’re getting started. Here’s a useful spreadsheet I made to show: the path of the files most important files and what they mean which tool creates which file Thanks Amr and Ahmed for helping me with this! Note that newer versions of OpenLANE have started numbering the filenames so I will update the spreadsheet in the future to reflect this.