OpenLANE makes a lot of output files! This can be quite confusing when you’re getting started. Here’s a useful spreadsheet I made to show: the path of the files most important files and what they mean which tool creates which file Thanks Amr and Ahmed for helping me with this! Note that newer versions of OpenLANE have started numbering the filenames so I will update the spreadsheet in the future to reflect this.

In this interview Thomas talks us through his Amateur satellite transceiver shuttle submission. We also discuss the differences between the Open Source tools and the industry standard ones he uses in his day job. Design repo: https://github.com/yrrapt/amsat_txrx_ic Caravel repo: https://github.com/yrrapt/caravel_amsat_txrx_ic Connect with Thomas on linkedin: https://www.linkedin.com/in/thomas-parry-60419468/

Almost exactly a year ago in March 2020 I started getting interested in Open Source ASIC tooling. I don’t remember exactly what sparked my interest, but I remember this talk by Tim Edwards at WOSH: Bootstrapping a real working design flow and sometime after seeing Adam Zeloof posting a picture of an ASIC implementation of pong. I began by investigating QFlow. The standard cells used by QFlow were from Oklahoma State University (OSU).

I’ve been wanting to try plotting or printing the GDS files from my first ASIC for a while, and finally I’ve had some time to have a play. I used KLayout because it’s easy to change colours, show and hide layers, and export to a high resolution PNG. I want to make a poster with 3 pictures inside: The whole chip, Zoomed into the VGA clock macro, Zoomed into the standard cells.