Tom Spyrou is a long time EDA developer who has worked at large and small companies. In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation. He was the original architect of PrimeTime STA algorithm. Manager of Cadence Common timing Engine and precursor to Open Access Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

I’m very pleased to get OSHWA certification for my ASIC clock. Who knows, maybe this is a world first! The clock was submitted as part of MPW1. We’re expecting silicon back in August/September, so it was time to get the PCB ready and try to source the other components! I started off by forking Sam Littlewood’s carrier board. This is a 4 layer board, but as I don’t need all the signals I was able to get it down to 2 layers for cheaper fabrication.

One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1. In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them. Dirk & Nguyen kindly allowed me to interview them about: their FABulous eFPGA framework, support for Yosys & NextPNR, parameterisation of the fabric, blockrams with OpenRAM, their MPW applications and previous tape-outs, and their experience with the open source tools.

After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better! One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have: removed the expiry date on the discord support, removed the expiry date on office hours.