I’ve been wanting to try plotting or printing the GDS files from my first ASIC for a while, and finally I’ve had some time to have a play. I used KLayout because it’s easy to change colours, show and hide layers, and export to a high resolution PNG. I want to make a poster with 3 pictures inside: The whole chip, Zoomed into the VGA clock macro, Zoomed into the standard cells.

When I was first testing my designs inside Caravel, I was quite confused about all the GPIO options. Each pin has a range of options that can be configured by firmware running on the RISCV processor. Each pin can be driven from the processor or your custom design. The outputs have separate output enable lines for bi-directional signalling. I put together an experiment where I tried the most important options and checked the results in a simulation.

The story of the first Open Source ASIC shuttle continues! A few of the applicants to the first shuttle were recently contacted by efabless - they had discovered some DRC issues that couldn’t be waived by the foundry. In my recent interview with Tim Edwards, he mentioned that Google are paying for a license of Calibre - another swiss army ASIC tool like Magic. This is to help make sure that the OpenLANE DRC hasn’t missed anything.

In this interview I talk with Tim Edwards from eFabless. He is their vice president of analog and platform. We mostly talked about what needs to happen before they send the final files to Skywater. A lot of the work is infrastructure: fetching files, compositing IDs, generating fill layers, a final DRC run.