We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come!
You can get all the details on all the projects from the
And see how I put the application together here.
Quad PWM FET Drivers
Framebufferless Video Core
This time around submission was a lot easier and nerve-wracking than MPW1.
Part of that was because I have the whole procedure pretty much automated with the multi project tools.
These tools can run a set of tests including:
- GDS size and layers
- Outputs Z when not selected
- Formal connectivity check
- Module tests
- Caravel context tests
- Module interface is correct
- Documentation is available
Then I can run a single command to copy all the GDS, LEF and generate the config file for OpenLANE.
./multi_tool.py --create-openlane-config --copy-gds --force-delete
Routing all the macros takes about 15 minutes, and running all the tests of all the designs takes about 60 minutes.
It wasn’t all smooth sailing, we had a few last minute changes including adding IRQs, a new user clock, and dealing with unwanted buffered outputs.
I put together a video to describe the process:
Awesome blender renders!
Course participant Maximo put together some lovely images here by converting the GDS to STL and then rendering inside blender.