People often use the terms RTL and HDL interchangably.

I see it in a bit of a different way, influenced by Mead & Conway’s book “Introduction to VLSI systems”. It’s more of a design methodology.

For reasons of speed and debugging, it makes sense to split up the data processing into smaller steps and buffer the results in registers (small memories usually made up of a stack of flip-flops). As the data flows between registers, it’s called register transfer level.

Here’s a quote from page 105 of the pdf of the book:

For a different viewpoint, this thread in stackexchange tries to answer the question - what is the difference between RTL and HDL.

I made a video about how flip-flops work, and cover a bit about the difference between combinatorial and sequential logic at the beginning.

Verilog and VHDL are both hardware description langauages (HDLs). They can describe all sorts of things, some of which are implementable by logic synthesis (ie synthesizable) and lots of things which are not. They can both describe netlists, ie the wiring together of pre-existing cells, and can also describe test harnesses and stimuli. The subset of these HDLs that is meant to describe real hardware behaviour (other than as netlist) is often referred to as RTL, but not all of this is synthesizable.

Course feedback

For a very long time I’ve been fascinated by ASICs and have been close to them in my professional life as well, but not really as much into the detail as I would want. It’s been a fascination since grad school at least, so I've been interested in seeing more open source alternatives crop up, and now with the skywater PDK and OpenLane it seemed like the right time. It’s still a bit hard to get the motivation to get started, it feels like a bit of a hurdle so when I saw this course I just jumped right on it. It felt like a perfect way to get started.

Klas Nordmark (digital course)