RTL
People often use the terms RTL and HDL interchangably.
I see it in a bit of a different way, influenced by Carver & Mead’s book “Introduction to VLSI systems”. It’s more of a design methodology.
For reasons of speed and debugging, it makes sense to split up the data processing into smaller steps and buffer the results in registers (small memories usually made up of a stack of flip-flops). As the data flows between registers, it’s called register transfer level.
Here’s a quote from page 105 of the pdf of the book:
For a different viewpoint, this thread in stackexchange tries to answer the question - what is the difference between RTL and HDL.
I made a video about how flip-flops work, and cover a bit about the difference between combinatorial and sequential logic at the beginning.
Course feedback
The Zero to ASIC course was great! Through this course I became more proficient with Verilog and started to not just appreciate, but actually enjoy the design verification! It offers the glimpse at the superpower too - seeing the traces of the original design in what used to be just squiggly lines of the masks before. Plus, I am getting my own piece of a silicon 🙂