Simulation lets us see the design working. It’s useful for debugging while designing and it can also be used to verify that the design is working correctly.
There are quite a few Open Source simulators available: Icarus Verilog, Verilator and recently CXXRTL.
We provide our HDL design and a testbench and we get back a data dump of the results of the simulation.
The data is usually in the form of a VCD (value change dump). This is a way of minimising file sizes, only when and what values changed are dumped. It’s not unusual to get multi-gigabyte dump files.
Here’s an example dump from the seven segment seconds example.
The testbench provides a clock and reset if required, and then runs the design for some time, capturing and maybe toggling various signals.
Above you can see the clock toggling too fast to see, and the digits slowly counting up to 9 and rolling over to 0. Underneath you can see the various elements of a 7 segment
display turning on and off to show the digit.
Traditionally testbenches have been written in Verilog, but I am now using a testing framework called coco-tb.
This makes it much easier to provide complex stimulus to the device under test (DUT).
Jump to 3:27 in this video to see a demonstration of cocotb being used to pass wavefiles through a filter implemented for an FPGA.
Simulation on its own can take us a fair way, but to be sure you should also verify your design.
Anybody who wants to learn about ASIC design who's never done it, this was a great introduction. I really enjoyed the course, this has been a great learning experience.