Synthesis
Synthesis is kind of analogous to the compilation process used for turning programming languages like C into binaries. The compiler knows how to read the language and maps it to the instructions we have available in the CPU.
Synthesis on the other hand reads the HDL and creates a netlist of wires and components that we have available in the target. In an FPGA those will be lookup tables (LUTs) and flip-flops. For ASIC, we have a large library of standard cells; things like AND, OR, NOT gates as well as lots of flip-flop variants.
It is a very complex and detailed process with lots of tuning options to trade off area vs speed. Until Claire Wolf wrote yosys, it was thought that only huge semiconducter companies had the resouces to write a synthesis tool.
Yosys is the Open Source tool that has been crucial in enabling the Open Source ASIC flow we have in OpenLane.
If things are going well, you normally don’t need to interact much with yosys. It will be part of a tool flow or Makefile.
If your design is broken in some way, then it is definitely worth learning how to use the built in show tool.
You can read the yosys show white paper here.
Course feedback
I hadn't done any verification before and it was a kind of light bulb moment of what it could bring to your confidence in a particular digital design.