Synthesis
Synthesis is kind of analogous to the compiler used for sequential programming languages like C. It reads the HDL and creates a netlist.
It is a very complex and detailed process. Until Claire Wolf wrote yosys, it was thought that only huge semiconducter companies had the resouces to write a synthesis tool.
yosys is the Open Source tool that has been crucial in enabling the Open Source ASIC flow we have in OpenLane.
If things are going well, you normally don’t need to interact much with yosys. It will be part of a tool flow or Makefile.
If your design is broken in some way, then it is definitely worth learning how to use the built in show tool.
You can read the white paper here
Course feedback
It is immensely helpful to have somebody who has gone through everything and know if something is not documented. You can read all day but you will not get the same out of it, so that was tremendously helpful.