Verification
Simulation offers us a way of checking the design is doing what we expect, but that is almost exactly why simulation on its own isn’t enough. When we simulate we are testing what we expect to happen. The problems happen when your design experiences something outside the expected.
There are a couple of extra tools we can use to increase our confidence that the design will work as designed.
Coverage
A coverage tool tests how complete your simulation or verification efforts actually are. I’m only aware of one free coverage tool we can use for HDL, and that’s YosysHQ’s mcy.
Formal Verification
Formal verification offers the opportunity to prove various properties of your design. For example, in the multi project harness, I wanted to prove that when the design is in reset the outputs are all undefined.
I can do that by adding an assertion to my design:
if(&reset)
assert(gpio_out == 10'bz);
Then I run a tool that uses a solver to prove that this assertion will always hold. If there is any way it can fail it will produce a short trace called a counter example. Even though this example is very simple it’s good to know that if I do something that accidentally messes up this property the assertion will fail, alerting me.
I have made a short course on Formal Verification you can follow here:
Course feedback
I wanted to get my hands dirty and I think your course sums up the whole experience from the ground up. You start by understanding how MOFETs work, get hands-on with Verilog and then all the way to the stage where you can be part of the ASIC shuttle.