LVS
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Layout vs Schematic is an important verification step.
After the design has been finished and we have the GDS2 files that we can send to the foundry, we want to check that the design is the same as the input that was described by the HDL.
In the OpenLane tool, at the end we have the LVS step. The netlist is extracted using Magic A tool called Netgen can compare this extracted netlist with the one we get after the synthesis step.
You will get some reports in the run directory. In the inverter example I have this file: results/lvs/inverter.lvs.log
The end of the file shows the input and output are equivalent.
Subcircuit pins:
Circuit 1: inverter |Circuit 2: inverter
-------------------------------------------|-------------------------------------------
in |in
out |out
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes inverter and inverter are equivalent.
Circuits match uniquely.
The most common types of LVS errors I’ve seen with OpenLane are:
- when power supplies aren’t connected for some reason,
- there is a short circuit during routing.
Course feedback
If you've got any interest in how the sausage is made you should get on the course and you should dig in and find out more. I mean this was the work of secret witches and wizards in mysterious cloaks casting strange incantations over a cauldron! This was all secret stuff and I love that this project is trying to do to silicon design what the open source community has been trying to do with software for the last 30 years. This feels like the next logical step and I think we'll look back and say well of course you can make your own chips that's just a thing and it will just be obvious and commonplace and I look forward to that.