Layout vs Schematic is an important verification step.

After the design has been finished and we have the GDS2 files that we can send to the foundry, we want to check that the design is the same as the input that was described by the HDL.

In the OpenLane tool, at the end we have the LVS step. The netlist is extracted using Magic A tool called Netgen can compare this extracted netlist with the one we get after the synthesis step.

You will get some reports in the run directory. In the inverter example I have this file: results/lvs/inverter.lvs.log

The end of the file shows the input and output are equivalent.

Subcircuit pins:
Circuit 1: inverter                        |Circuit 2: inverter                        
-------------------------------------------|-------------------------------------------
in                                         |in                                         
out                                        |out                                        
VGND                                       |VGND                                       
VPWR                                       |VPWR                                       
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes inverter and inverter are equivalent.
Circuits match uniquely.