Place and Route are 2 steps in the automated process of turning some HDL into GDS2 files.
We will look at how OpenLane does these steps using the seven segment seconds example.
I have used my presentation tools to generate these images.
Placement is done in two steps, coarse and fine. The coarse step puts the standard cells in roughly the right place.
The file shown is replace.def.
The fine step aligns the cells to the grid and makes sure they don’t overlap.
The file shown is placement.def.
After the cells are in the correct places, the routing of clocks, power and signals can start.
Here is the power distribution, the file shown is pdn.net. You can see thick horizontal metal lines carrying power and ground. Then there are the thinner horizontal lines
that connect to the top and bottom of the standard cells. That’s why all the standard cells have the power and ground at the top and bottom at a fixed distance.
And finally, here is a zoomed image of the same design, but showing the routing wires on the metal layers. This file is routing/design.def
Clock Tree Synthesis
I don’t have a good picture of CTS, but it’s worth mentioning here. The clock (and reset) are important and heavily loaded signals.
The clock especially is probably driving thousands of gates. Each of these gates has a small capacitance that requires some effort to charge or discharge.
For this reason the clock line is treated specially and CTS makes sure the clock drive strength is strong enough by adding special clock buffer standard cells.
It’s a fairly daunting prospect going into something like an ASIC, but I feel confident now that I could pick another project up and go from the start with the Verilog and end up with something that will hopefully work.