Review of 2022 and aims for 2023
Welcome to my highlights from 2022! It was a big year for open-source silicon, especially the Zero to ASIC course and TinyTapeout. Let’s look at some of the highlights and then some aims for 2023.
Here are a few of the highlights:
- Four Zero to ASIC course tapeouts: MPW5, MPW6, MPW7, and MPW8
- Rolled out TinyTapeout 01 and 02, helping nearly 250 people tapeout their designs,
- I personally submitted my 19th tapeout
- Presented and hosted a TinyTapeout workshop at the Hackaday SuperCon in Novemeber 2022. Met tons of people, including Sam Zeloof @szeloof.
- YouTube Channel had 82k views and 2.5k new subscribers
- Introduced Siliwiz
Zero to ASIC course Tapeouts
The Zero to ASIC course continued to grow, we now have 280 students and made submissions to four multi-project wafers (MPW).
Additionally, I received MPW1 and MPW2, which I’m currently bringing up.
Personally I learned a lot about ASIC design, reaching my 19th tapeout.
Expanding Access to Open-Source Silicon
In addition to Zero to ASIC, I also launched the TinyTapeout program.
TinyTapeout further lowers the barrier to entry to silicon. I was so excited to see kids submitting designs. The youngest submitter so far is 4-year-old Ms. Nguyen-Taylor with “Heart Zoe Mom Dad”.
It was also great to introduce SiliWiz, enabling people to get real-time feedback while designing circuits in silicon.
Keep an eye out for TinyTapeout 03 and further updates on Siliwiz in 2023!
In 2022 my top social media posts were:
- My VGA clock submitted on MPW1
- Living in a world where my 9-year-old can design a chip
- Closing out TinyTapeout 02
Clarifying My Roles
There had been some confusion about my specific roles in the open-silicon community.
Currently I am working with
- Yosys HQ on training, marketing, and sales
- EFabless on community management and communications
- Chipflow on communications and building a system-on-chip with Amaranth
- Zero to ASIC course and TinyTapeout to lower the barrier to ASIC design and help people get to their first tapeout
There has been some confusion between the Zero to ASIC course and the ZeroASIC startup. I’m not involved in their efforts, but feel free to check out their site! They’re developing a great Verilog-to-GDS flow called silicon compiler.
Goals for 2023
Here are some of the goals I’d like to accomplish in 2023 with the community:
- Help the community submit 1000 more designs for fab!
- Continue contributing to open-source EDAs for FPGAs and ASICs
- Have our first European tapeout on IHP
- Get more chips working: complete the MPW2 bringup, as well as MPW3, 4, and 5.
- Submit my first analog design and assemble documentation to help others do the same
- Update the course, including more information about timing closure. This is a critical aspect of ASIC design, and there’s not much information out there.
- Visit IHP and tour their foundry
- Meet with Tomas Aidukas to do an x-ray tomography scan of the MPW1 designs
- Run TinyTapeout 03, 04, 05, and 06, with improvements to the scanchain multiplexer. I’m also keen to start working wiht more universities and schools.
- Taping out with SkyWater 90nm process
- Make the Zero to ASIC course more accessible, for example with the low-cost ticket grant
A Few Thoughts on Open-Source Silicon
- It’s hard to admit Moore’s law is slowing down, but perhaps this can be a good push towards more innovation
- There’s still lots of room for innovation, such as advanced chip packaging and in application specific designs
- So few people have access to semiconductors despire their ubiquity. As we lower the barrier to silicon, we can hopefully bring even more creativity to the problems.