The floorplanning stage is where OpenLane decides how big an area we need to fit everything in. All the required standard cells are placed in the bottom left corner, ready for the place and route stage.

All the little rectangles in the centre are called tap cells. They make sure the MOSFETs work correctly by connecting the P doped substrate to ground and the N-wells (that insulate the P-type MOSFETS) to power.

The slightly bigger rectangles at the edges are decoupling capacitors. After the routing is finished, any spare space is filled up with decoupling capacitors. The job of these capacitors is to make sure that all the cells get a nice smooth power supply.

Course feedback

I've always looked at Magic and it was basically impenetrable to me. So I was really happy to learn how to actually use it and understand how to make an ASIC. I found found the course materials very easy to follow and the discord conversations were also very useful.

Robert Baruch (digital course)