SiliWiz will help you get a basic understanding of how semiconductors work and are manufactured at a fundamental level. It’s a free and open source tool that you can play with in your browser. Aims Draw your own logic gate and understand how that gate would be manufactured in a foundry. Learn how the gate is built out of the fundamental circuit elements used in chip design Understand how the drawings are used to manufacture the chip Be aware of some of SiliWiz’s limitations and simplifications Lessons We have a set of free lessons that guide you through from drawing and simulating resistors all the way up to a CMOS inverter.

Welcome to the September 2022 monthly update! Here are the main topics from last month: MPW7 submission, MPW2 updates, Job posting at E-Fabless, New videos, Is it the end for UVM? and Rendering GDS files with Blender or in your browser MPW7 The deadline for MPW7 was the 14th of September and the Zero to ASIC course submitted another set of projects. Special shout out to Farhad, Peng and James who are all first time tape outs on the project.

The 3D structures created within a silicon die are spectacular to see. Thanks to Maximo (@maxiborga on Twitter), there’s now a video for 3D rendering ASIC designs enabling anyone to convert their ASIC design into a beautiful 3D rendering. 3D-rendered chip in Blender His walkthrough shows how to convert GDS to STL files, enabling you to import the files in image editing software like Blender. By following along the video, I was able to render my first ever GDS, an inverter I created back in 2020

ASICs pack in billions of transistors per square centimeter, making their construction and functionality impossible to understand with the naked eye. In fact, the upcoming 2 nanometer technology will be so small* that the transistor dimensions will only be 20X larger than an individual atom. Wouldn’t it be great to see how ASICs are built in 3D at a scale that our bulky human hands can appreciate? Well wait no longer!

In this interview with Professor James Stine, we talk about: Why is Open Source the key to innovation? What do students struggle with most when learning to design standard cell libraries? What are the biggest misconceptions engineers have about standard cells? What’s James’ tool flow? How many cells are needed to make a library? Why do we need another library for Global Foundries (GF) 180? How far are open source tools from commercial tools?

We submitted for MPW7! I am particularly excited about this submission because we were able to submit the Zero to ASIC course designs as well as the first Tiny Tapeout design. MPW7 has by far had the most submissions of the MPW shuttles so far with 72 submitted projects as of 13 September. Congratulations to everyone on the course submission! We had 9 projects from the course, with 1 demo arbitrary function generator from me, a 32-bit RISC-V based processor by Farhad, an in silicon version of Conway’s Game of Life from Uri and a Spiking Neural Network (SNN) accelerator by Peng Zhou.

Following my interview with Teo on optimising hardware adders, I thought it would be a great project to tapeout on MPW6. I wrote about the process on twitter: I'm working on putting @td_ene 's adder work onto MPW6. Work in progress repo here: https://t.co/OBg8jQG1HJ It was very easy to generate the adders, but I'm getting stuck on instrumenting them. I need to measure the performance inside the chip to get accurate results.

We submitted for MPW6! We had 4 submissions from the course, the shared SRAM infrastructure, and I did some work on instrumenting Teo’s hardware adders. Congratulations to: Zorkan ERKAN Emre Hepsag Gregory Kielian Jason K. Eshraghian for getting your first ASIC designs on the submission! We also had some people from the course make personal applications for a whole chip: Shumpei Kawasaki - MARMOT SOC Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses, Proppy - HSV Mixer Here’s the github repo for the group submission and the Efabless project.

Proppy has been doing some great work with preparing the open source ASIC tools to work inside Jupyter notebooks. This means that you can now experiment with simulation and ASIC hardening without needing to download or configure the tools. I think this is going to be of great importance for academia and education: Now when people publish papers they can include a link to a notebook that reproduces the published results.