We submitted for MPW5! We had 8 submissions from the course, the shared SRAM infrastructure, and I updated my demo designs. We also had some people from the course make personal applications for a whole chip: Steve & Zhenle - PSRAM (HyperRAM) interface with an ACORN PRNG, Q3K - simple, microcontroller-style SoC based around a Lanai core, Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses, Zbigniew - A rendering circuit for three blobs and a playable tetris clone.

Yes! All the designs I submitted to MPW1 are working: ✅ 7 segment display ✅ TPM2137 CTF ✅ WS2812 led driver ✅ VGA clock ✅ Multiplexor I put together a video to demonstrate them all: The 4 other designs that were part of this submission were made by friends who I’ve now sent samples to. It’s looking likely that everyone’s designs will work. Bringup You can read more about the bringup process here, and see the repository with firmware here: https://github.

I submitted my first ASIC designs to the free Google shuttle in December of 2020. In October 2021, we heard there were serious clock related problems with the management area of the chip due to issues with the toolchain. It seemed unlikely that anyone would be able to get anything beyond a single blinking LED from MPW1. The hold violations in the management system meant that the PicoRV32 cpu couldn’t run and setup the GPIOs.

We submitted for MPW4! I was pretty pleased we managed to get so much in with such little time and for a tapeout date of New Year’s Eve. We had 9 submissions from the course, with 1 demo project from me and a new version of Maximo’s hacksoc. Uri submitted 3 designs including some custom standard cells in the shape of skulls! We also implemented the shared SRAM, which means that the group projects have access to a local fast memory (like a blockram on an FPGA).

We submitted for MPW3! The tapeout date was delayed by a couple of weeks due to issues with the toolchain. We had 7 new submissions from the course, 4 repeats from MPW1 and 2 with fixed clock trees, a new wishbone demo from me and the OpenRAM block. We also had some people course make personal applications for a whole chip: Exor’s project contains two sudoku accelerator modules on the wishbone bus: https://platform.

MPW1 seems an age ago, we submitted in December 2020, but it needed some last minute DRC fixes in February. Silicon was received a few weeks ago, and unfortunately we have some serious issues that will prevent most designs from working. This appears to be due to a bad clock tree in the management section of the chip. Additionally, OpenSTA, the tool meant to verify the clock tree was also misconfigured.

We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come! You can get all the details on all the projects submitted to MPW2 here. And see how I put the application together here, with the repo here. Project listing RGB Mixer Author: Matt Venn Github: https://github.com/mattvenn/wrapped_rgb_mixer/tree/caravel-mpw-two-c Description: reads 3 encoders and generates PWM signals to drive an RGB LED Frequency counter Author: Matt Venn Github: https://github.

Efabless have announced MPW2! The closing date is the 18th of June. The biggest changes are: OpenLANE ASIC flow updated to rc0.15 Caravel has become caravel_user_project at the mpw-two-c tag: smaller repo size includes a ‘Caravel Lite’ submodule new IRQ ports logic analyser registers renamed An alternative analogue specific ‘Caravan’ harness The submission process has been streamlined to make it faster and easier to submit You can browse the current applications here: https://platform.

The story of the first Open Source ASIC shuttle continues! A few of the applicants to the first shuttle were recently contacted by efabless - they had discovered some DRC issues that couldn’t be waived by the foundry. In my recent interview with Tim Edwards, he mentioned that Google are paying for a license of Calibre - another swiss army ASIC tool like Magic. This is to help make sure that the OpenLANE DRC hasn’t missed anything.

Wow! What a journey. I’m very happy to announce our submission is in and accepted. Now we have a long wait to see if it works! (it does! Jump to the end for an update). Here’s a picture of the final design. The outer edge and the block at the bottom are all part of Caravel, the standard chip format that everyone on the shuttle has to use. It includes a RISCV processor, RAM, UART, a wishbone bus and more.

The Google/Skywater Shuttle has about 10 square mm of space for your project. This sounds tiny but is actually HUGE for many beginner projects. Read this post to find out what you could fit in the user space. For the Zero to ASIC course, I want to aggregate all your designs together into that area, so we need to do some extra bits: Multiplex all the inputs and outputs of your project to the GPIO pins of the Caravel harness.